In digital communications by means of satellites, QPSK is generally used to modulate a carrier wave according to a digital baseband signal. On the receive side, the baseband signal is recovered from the received QPSK modulated carrier wave by a QPSK demodulator. In such a QPSK demodulator, clock recovery is a very important technology to obtain accurate symbol identification. For this accurate clock recovery, various circuits have been proposed.
FIG. 1 shows an example of a conventional clock recovery circuit in a QPSK demodulator. Here, assuming that the demodulated baseband signal D(n) corresponding to one of I channel and Q channel is input to an input terminal A and the QPSK demodulator operates at a sampling frequency N-times the symbol rate (N=2k; where k=1, 2, . . . ). A signal polarity change detector 21 detects the polarity change of the input signal from the demodulated baseband signal D(n) and the output D(n-N) of a one-symbol delay circuit 22 to make a selector 242 work.
When there is a change in signal polarity, it is estimated that the signal D(n-N/2) which is an output of a 1/2 symbol delay circuit 23 was a near-zero value. Therefore, by using this near-zero value as the amount of deviation from zero, a Phase-Locked Loop (PLL) circuit for controlling the phase of the sampling clock is formed, thereby implementing D(n-N/2)=0 and allowing the output of VCO (Voltage Controlled Oscillator) to be synchronized with the zero-cross point of the demodulated baseband signal, that is, clock recovery is carried out.
The operation of the signal polarity change detector 21 is explained with reference to the flowchart in FIG. 2. First, in step S1, it determines whether there is a polarity change or not. That is, the presence or absence of polarity change is detected from D(n) and D(n-N). If there is a polarity change, it means that there was a zero-cross point from one symbol prior and on. Moreover, it can be guessed that the value of D(n-N/2) is a near-zero value which can be taken as the amount of deviation from zero. The relationship between the deviation direction of the sampling timing of D(n-N/2) from the zero-cross point and the polarity of D(n-N/2) depends on the polarity change direction for the amount of one-symbol time. Therefore, the signal polarity change detector 21 can control the selector 242 such that one of D(n-N/2) and -D(n-N/2) is selected as the feedback value of the PLL circuit based on the polarity change direction information, where -D(n-N/2) is obtained through an inverter 241 which inverts D(n-N/2). That is, when the polarity changes from positive to negative, the output, -D(n-N/2), of the inverter 241 is selected (steps S4), and when the polarity changes from negative to positive, the output, D(n-N/2), of the 1/2-symbol delay circuit 23 is selected (steps S4).
No polarity change in step S1 means that there is no zero-cross point between symbols. In this case, the selector 242 is controlled to make the feedback value zero, to fix the sampling clock (step S3).
The feedback value selected by the selector 242 is input to the VCO 26 through a loop filter 25. The output of the VCO 26 can be taken as a clock signal which is synchronized with the symbol clock. Therefore, a clock recovery feedback system can be made by using the clock signal as a sampling clock.
However, in such a clock recovery circuit, clock recovery cannot be carried out accurately in a .pi./4 shift QPSK modulation system.
The .pi./4 shift QPSK is a kind of QPSK system but having the same constellation as the 8-phase PSK system, as shown in FIG. 3. For example, in cases where a bit stream to be transmitted is x.sub.0, x.sub.1, . . . , X.sub.n-2, X.sub.n-1 (where n is an even number), a symbol stream is constructed with pairs of bits, such as (x.sub.0, x.sub.1), (x.sub.2, x.sub.3), . . . , (x.sub.n-2, x.sub.n-1). Here, the bits which are transmitted first in respective symbols are regarded as the I channel and the other bits as the Q channel. In the QPSK modulation, the symbols are mapped to (1, 1), (-1, 1), (-1, -1), and (1, -1). On the other hand, in .pi./4 shift QPSK modulation, the odd symbols are mapped to (1, 1), (-1, 1), (-1, -1), and (1, -1), and the even symbols are shifted by .pi./4 to be mapped to (0, .sqroot.2), (-.sqroot.2, 0), (0, -.sqroot.2), and (.sqroot.2, 0). In shifting by .pi./4, the method of shifting each symbol by +.pi./4 may be employed.
Since the odd symbol phase is shifted by .pi./4 in the .pi./4 shift QPSK modulation, it is reverse-shifted by .pi./4 in the .pi./4 shift QPSK demodulation. In cases where there is a polarity change between the demodulated symbols, the 1/2-symbol prior value deviates from the zero-cross point by .pi./8 in phase compared to that in the QPSK. Moreover, the direction of this phase deviation depends on the transition of the signal state as well. Therefore, the accurate clock recovery cannot be achieved by using the 1/2-symbol prior value which is estimated to be a near-zero value when there was a polarity change between the demodulated symbols.
An object of the present invention is to provide a clock recovery circuit which can achieve accurate clock recovery in the .pi./4 shift QPSK demodulator.